this datasheet contains new product information. anachip corp. re serves the rights to modify the product specification without notice. no liability is assumed as a result of the use of this product. no rights under any patent accompany the sale of the product. rev. 1.0 dec 16, 2004 1/10 pa7572 peel array? programmable electrically erasable logic array versatile logic array architecture - 24 i/os, 14 inputs, 60 registers/latches - up to 72 logic cell output functions - pla structure with true product-term sharing - logic functions and registers can be i/o-buried high-speed commercial and industrial versions - as fast as 13ns/20ns (tpdi/tpdx), 66.6mhz (f max ) - industrial grade available for 4.5 to 5.5v v cc and -40 to +85 c temperatures ideal for combinatorial, synchronous and asynchronous logic applications - integration of multiple plds and random logic - buried counters, complex state-machines - comparators, decoders, other wide-gate functions cmos electrically erasable technology - reprogrammable in 40-pin dip, 44-pin plcc and tqfp packages flexible logic cell - up to 3 output functions per logic cell - d,t and jk registers with special features - independent or global clocks, resets, presets, clock polarity and output enables - sum-of-products logic for output enables development and programmer support - ict place development software - fitters for abel, cupl and other software - programming support by popular third-party programmers general description the pa7572 is a member of the programmable electrically erasable logic (peel?) arra y family based on anachip?s cmos eeprom technology. peel? arrays free designers from the limitations of ordinary plds by providing the architectural flexibility and speed needed for today?s programmable logic designs. the pa7572 offers a versatile logic array architecture with 24 i/o pins, 14 input pins and 60 registers/latches ( 24 buried logic cells, 12 input registers/latches, 24 buried i/o registers/latches). its logic array implements 100 sum-of-products logic functions divided into two groups each serving 12 logic cells. each group shares half (60) of the 120 product-terms available. the pa7572?s logic and i/o cells (lccs, iocs) are extremely flexible with up to three output functions per cell (a total of 72 for all 24 logic cells). cells are configurable as d, t, and jk registers with independent or global clocks, resets, presets, clock polarit y, and other features, making the pa7572 suitable for a variety of combinatorial, synchronous and asynchronous logic applications. the pa7572 supports speeds as fast as 13ns/20ns (tpdi/tpdx) and 66.6mhz (f max ) at moderate power consumption 140ma (100ma typical). packaging includes 40-pin dip and 44-pin plcc (see figure 1). anachip and popular third-party development t ool manufacturers provide development and programming support for the pa7572. figure 1. pin configuration 08-15-001a dip (600 mil) i/clk1 1 i 2 i 3 i 4 i/o 5 i/o 6 i/o 7 i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 vcc 40 i 39 i 38 i 37 i/o 36 i/o 35 i/o 34 i/o 33 i/o 32 i/o 31 i/o 30 i/o 29 i/o 13 i/o 14 i/o 15 i/o 16 i 17 i 18 i 19 gnd 20 i/o 28 i/o 27 i/o 26 i/o 25 i 24 i 23 i 22 i/c lk2 21 7 i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 18 i/o 19 i 20 i 21 i 22 gnd 23 gnd 24 i/c lk2 4 i 3 i 2 i/c lk1 1 vcc 44 vcc 43 i 42 i plcc 39 gnd 38 i/o 37 i/o 36 i/o 35 i/o 34 i/o 33 i/o 6 i/o 5 i 14 i/o 15 i/o 16 i/o 17 gnd 25 i 26 i 27 i 28 i/o 32 i/o 31 i/o 30 i/o 29 i/o 41 i 40 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 12 i/o 13 i 14 i 15 i 16 gnd 17 gnd 18 i/clk2 42 i 41 i 40 i/c lk1 39 vcc 38 vcc 37 i 36 i tqfp 33 gnd 32 i/o 31 i/o 30 i/o 29 i/o 28 i/o 27 i/o 44 i/o 43 i 8 i/o 9 i/o 10 i/o 11 gnd 19 i 20 i 21 i 22 i/o 26 i/o 25 i/o 24 i/o 23 i/o 35 i 34 i/o figure 2. block diagram input cells (inc) 12 input pins 2 input/ global clock pins global cells 2 12 i/o cells (ioc) logic control cells (lcc) 24 24 24 24 a b c d 124 (62x2) array inputs true and complement buried logic 4 sum terms 5 product terms for global cells 24 logic control cells up to 3 output functions per cell (72 total output functions possible) logic functions to i/o cells 24 i/o pins 96 sum terms (four per lcc) logic array pa7572 i i i i/o i/o i/o i/o i/o i/o i i i i i i i/o i/o i/o i/o i/o i/o i i i vcc i/clk 2 gnd i/c lk i/o i/o i/o i/o i/o i/o global cells input cells i/o cells i/o i/o i/o i/o i/o i/o logic control cells 08-15-002a to find out if the package you need is available, contact customer service
anachip corp. www.anachip.com.tw rev. 1.0 dec 16, 2004 2/10 inside the logic array the heart of the peel? array architecture is based on a logic array structure similar to that of a pla (programmable and, programmable or). the logic array implements all logic functions and provides interconnection and control of the cells. in the pa7572 peel? array, 62 inputs are available into the array from the i/o cells, inputs cells and input/global-clock pins. all inputs provide both true and complement signals, which can be programmed to any product term in the array. the pa7572 peel? arrays contains 124 product terms. all product terms (with the exception of certain ones fed to the global cells) can be programmably connected to any of the sum-terms of the logic control cells (four sum-terms per logic control cell). product-terms and sum-terms are also routed to the global cells for control purposes. figure 3 shows a detailed view of t he logic array structure. from io cells (ioc,inc, i/clk) from logic control cells (lcc) to global cells 62 array inputs 125 product terms to logic control cells (lcc) 100 sum terms pa7572 logic array 08-15-003a figure 3. pa 7572 logic array true product-term sharing the peel? logic array provi des several advantages over common pld logic arrays. first, it allows for true product- term sharing, not simply product-term steering, as com- monly found in other cplds. product term sharing ensures that product-terms are used where they are needed and not left unutilized or duplicated. secondly, the sum-of- products functions provided to the logic cells can be used for clocks, resets, presets and output enables instead of just simple product-term control. the peel? logic array can also implement logic functions with many product terms within a single-level delay. for example a 16-bit comparator needs 32 shared product terms to implement 16 exclusive-or functions. the peel? logic array easily handles this in a single level delay. other plds/cplds either run out of product-terms or require expanders or additional logic levels that often slow performance and skew timing. logic control cell (lcc) logic control cells (lcc) are used to allocate and control the logic functions created in the logic array. each lcc has four primary inputs and three outputs. the inputs to each lcc are complete sum-of-product logic functions from the array, which can be used to implement combinatorial and sequential logic functions, and to control lc c registers and i/o cell output enables. a b c d reg d,t,j k r p q mux system clock preset reset on/off regtype from global cell mux mux to array to i/o cell from array 08-15-004a figure 4. logic control cell block diagram as shown in figure 4, the lc c is made up of three signal routing multiplexers and a versatile register with synchronous or asynchronous d, t, or jk registers (clocked -sr registers, which are a subset of jk, are also possible). see figure 5. eeprom memory cells are used for programming the desired configuration. four su m-of-product logic functions (sum terms a, b, c and d) ar e fed into each lcc from the logic array. each sum term can be selectively used for multiple functions as listed below. to find out if the package you need is available, contact customer service
anachip corp. www.anachip.com.tw rev. 1.0 dec 16, 2004 3/10 sum-a = d, t, j or sum-a sum-b = preset, k or sum-b sum-c = reset, clock, sum-c sum-d = clock, output enable, sum-d d r p q d register q = d after clocked best for storage, simple counters, shifters and state machines with few hold (loop) conditions. t r p q t register q toggles when t = 1 q holds when t = 0 best for wide binary counters (saves product terms) and state machines with many hold (loop) conditions. jk register q toggles when j/k = 1/1 q holds when j/k = 0/0 q = 1 when j/k = 1/0 q = 0 when j/k = 0/1 combines features of both d and t registers. j r p q k 08-15-005a figure 5. lcc register types sum-a can serve as the d, t, or j input of the register or a combinatorial path. sum-b can serve as the k input, or the preset to the register, or a combinatorial path. sum-c can be the clock, the reset to the register, or a combinatorial path. sum-d can be the clock to the register, the output enable for the connected i/o cell, or an internal feedback node. note that the sums cont rolling clocks, resets, presets and output enables are complete sum-of-product functions, not just product terms as with most other plds. this also means that any input or i/o pin can be used as a clock or other control function. several signals from the global cell are provided primarily for synchronous (global) register control. the global cell signals are routed to all lccs. these signals include a high-speed clock of positive or negative polarity, global preset and reset, and a special register-type control that selectively allows dynamic switching of register type. this last feature is especially useful for saving product terms when implementing loadable counters and state machines by dynamically switching from d-type registers to load and t-type registers to count (see figure 9). multiple outputs per logic cell an important feature of the logi c control cell is its capability to have multiple output functions per cell, each operating independently. as shown in figure 4, two of the three outputs can select the q output from the register or the sum a, b or c combinatorial paths. thus, one lcc output can be registered, one combinatorial and the third, an output enable, or an additional buried logic function. the multi- function peel? array logic cells are equivalent to two or three macrocells of other plds, which have one output per cell. they also allow registers to be truly buried from i/o pins without limiting them to input-only (see figure 8 & figure 9). i/o cell (ioc) input cell (inc) reg/ latch q mux input to array input cell clock from global cell mux from logic control cell a,b,c or q mux mux 1 0 d i/o pin mux to array reg/ latch q input cell clock from global cell input input 08-15-006a figure 6. input and i/o cell block diagrams ioc/inc register q = d after rising edge of clock holds until next rising edge ioc/inc latch q = l when clock is high holds value when clock is low lq d q 08-15-007a figure 7. ioc/inc regi ster configurations to find out if the package you need is available, contact customer service
anachip corp. www.anachip.com.tw rev. 1.0 dec 16, 2004 4/10 input cells (inc) input cells (inc) are included on dedicated input pins. the block diagram of the inc is shown in figure 6. each inc consists of a multiplexer and a register/transparent latch, which can be clocked from vari ous sources selected by the global cell (see figure 7). the register is rising edge clocked. the latch is transparent when the clock is high and latched on the clock?s falling edge. the register/ latch can also be bypassed for a non-registered input. i/o cell (ioc) all peel? arrays have i/o cells (ioc) as shown above in figure 6. inputs to the iocs can be fed from any of the lccs in the array. each ioc consists of routing and control multiplexers, an input register/transparent latch, a three- state buffer and an output polarit y control. the register/ latch can be clocked from a va riety of sources determined by the global cell. it can also be bypassed for a non- registered input. the pa7572 allows the use of sum-d as a feedback to the array when the i/o pin is a dedicated output. this allows for additional buried registers and logic paths. (see figure 8 and figure 9). i/o with independent output enable i/o qd input with optional register/latch a b c d 1 2 oe dq 08-15-008a figure 8. lcc & ioc with two outputs a b c d output 1 2 3 buried register or logic paths qd dq 08-15-009a figure 9. lcc & ioc with three outputs global cells the global cells, shown in figure 10, are used to direct global clock signals and/or control terms to the lccs, iocs and incs. the global cells allow a clock to be selected from the clk1 pin, clk2 pin, or a product term from the logic array (pclk). they also provide polarity control for inc and ioc clocks enabling rising or falling clock edges for input registers/latches. note that eac h individual lcc clock has its own polarity control. the global cell for lccs includes sum- of-products control terms for global reset and preset, and a fast product term control for lcc register-type, used to save product terms for loadable counters and state machines (see figure 11). the pa7572 provides two global cells that divide the lcc and iocs into groups, a and b. half of the lccs and iocs use global cell a, half use global cell b. this means that two high-speed global clocks can be used among the lccs. global cell: lcc & ioc mux mux clk1 clk2 pclk reg-type preset reset lcc resets lcc presets lcc reg-type ioc clocks lcc clocks global cell: inc mux clk1 clk2 pclk inc clocks group a & b 08-15-010a figure 10. global cells register type change feature global cell can dynamically change user- selected lcc registers from d to t or from d to jk. this saves product terms for loadable counters or state machines. use as d register to load, use as t or jk to count. timing allows dynamic operation. t r p q d r p q reg-type from global cell example: product terms for 10 bit loadable binary counter d uses 57 product terms (47 count, 10 load) t uses 30 product terms (10 count, 20 load) d/t uses 20 product terms (10 count, 10 load) 08-15-011a figure 11. register ty pe change feature to find out if the package you need is available, contact customer service
anachip corp. www.anachip.com.tw rev. 1.0 dec 16, 2004 5/10 peel? array development support development support for peel ? arrays is provided by anachip and manufacturers of popular development tools. anachip offers the powerful place development software (free to qualified pld designers). the place software includes an architectural editor, logic compiler, waveform simulator, documentation utility and a programmer interface. the place editor graphically illustrates and controls the peel? array?s architecture, making the overall design easy to understand, while allowing the effectiveness of boolean logic equations, state machine design and truth table entry. the place compiler performs logic transformation and reduction, making it possible to specify equations in almost any fashion and fit the most logic possible in every design. place also provides a multi-level logic simulator allowing external and internal signals to be simulated and analyzed via a waveform display.(see figure 12, figure 13, figure 14) figure 12. place arch itectural editor peel? array development is also supported by popular development tools, such as abel and cupl, via ict?s peel? array fitters. a special smart translator utility adds the capability to directly c onvert jedec f iles for other devices into equivalent jedec files for pin-compatible peel? arrays. programming peel? arrays are ee-reprogrammable in all package types, plastic-dip, plcc and soic. this makes them an ideal development vehicle for the lab. ee- reprogrammability is also usef ul for production, allowing unexpected changes to be made quickly and without waste. programming of peel? a rrays is supported by many popular third party programmers. design security and signature word the peel? arrays provide a special eeprom security bit that prevents unauthorized readi ng or copying of designs. once set, the programmed bits of the peel? arrays cannot be accessed until the entire chip has been electrically erased. another programming feature, signature word, allows a user-definable code to be programmed into the peel? array. the code can be read back even after the security bi t has been set. the signature word can be used to identify the pattern programmed in the device or to record the design revision. figure 13. place lc c and ioc screen figure 14. place simulator screen to find out if the package you need is available, contact customer service
anachip corp. www.anachip.com.tw rev. 1.0 dec 16, 2004 6/10 this device has been designed and tested for the specified operating ranges. improper operation outside of these levels is not guaranteed. exposure to absolute maximum ratings may cause permanent damage. table 1. absolute maximum ratings symbol parameter conditions ratings unit v cc supply voltage relative to ground -0.5 to + 7.0 v v i , v o voltage applied to any pin relative to ground 1 -0.5 to v cc + 0.6 v i o output current per pin (i ol , i oh ) 25 ma t st storage temperature -65 to + 150 c t lt lead temperature soldering 10 seconds +300 c table 2. operating ranges symbol parameter conditions min max unit commercial 4.75 5.25 v cc supply voltage industrial 4.5 5.5 v commercial 0 +70 t a ambient temperature industrial -40 +85 c t r clock rise time see note 2 20 ns t f clock fall time see note 2 20 ns t rvcc v cc rise time see note 2 250 ms table 3. d.c. electri cal characteristics over the operating range symbol parameter conditions min max unit v oh output high voltage - ttl v cc = min, i oh = -4.0ma 2.4 v v ohc output high voltage - cmos v cc = min, i oh = -10a v cc - 0.3 v v ol output low voltage - ttl v cc = min, i ol = 16ma 0.5 v v olc output low voltage - cmos v cc = min, i ol = -10a 0.15 v v ih input high level 2.0 v cc + 0.3 v v il input low level -0.3 0.8 v i il input leakage current v cc = max, gnd ?v in ?v cc 10 a i oz output leakage current i/o = high-z, gnd ?v o ?v cc 10 a i sc output short circuit current 4 v cc = 5v, v o = 0.5v, ta= 25c -30 -120 ma -20 75 i cc 11 v cc current v in = 0v or v cc 3,11 f = 25mhz all outputs disabled 4 i-20 50 (typ.) 18 85 ma c in 7 input capacitance 5 6 pf c out 7 output capacitance 5 t a = 25c, v cc = 5.0v @ f = 1 mhz 12 pf to find out if the package you need is available, contact customer service
anachip corp. www.anachip.com.tw rev. 1.0 dec 16, 2004 7/10 table 4. a.c electrical ch aracteristics combinatorial over the operating range -20/i-20 symbol parameter 6,12 min max unit t pdi propagation delay internal (t al + t lc ) 13 ns t pdx propagation delay external (t ia + t al +t lc + t lo ) 20 ns t ia input or i/o pin to array input 2 ns t al array input to lcc 12 ns t lc lcc input to lcc output 10 1 ns t lo lcc output to output pin 5 ns t od , t oe output disable, enable from lcc output 7 5 ns t ox output disable, enable from input pin 7 20 ns this device has been designed and tested for the recommended operating conditions. proper operation outside of these levels is not guaranteed. exposure to absolute maximum ratings may cause permanent damage figure 15. combinatorial timing - waveforms and block diagram to find out if the package you need is available, contact customer service
anachip corp. www.anachip.com.tw rev. 1.0 dec 16, 2004 8/10 table 5. a.c. electrical characteristics sequential -20/i-20 symbol parameter 6,1 min max unit t sci internal set-up to system clock 8 - lcc 14 (t al + t sk + t lc - t ck ) 8 ns t scx input 16 (ext.) set-up to system clock, - lcc (t ia + t sci ) 10 ns t coi system-clock to array int. - lcc/ioc/inc 14 (t ck +t lc ) 7 ns t cox system-clock to output ext. - lcc (t coi + t lo ) 12 ns t hx input hold time from system clock - lcc 0 ns t sk lcc input set-up to async. clock 13 - lcc 1 ns t ak clock at lcc or ioc - lcc output 1 ns t hk lcc input hold time from system clock - lcc 4 ns t si input set-up to system clock - ioc/inc 14 (t sk - t ck ) 0 ns t hi input hold time from system clock - ioc/inc (t sk - t ck ) 5 ns t pk array input to ioc pclk clock 9 ns t spi input set-up to pclk clock 17 - ioc/inc (t sk -t pk -t ia ) 0 ns t hpi input hold from pclk clock 17 - ioc/inc (t pk +t ia -t sk ) 10 ns t sd input set-up to system clock - ioc/inc sum-d ( t ia + t al + t lc + t sk - t ck ) 10 ns t hd input hold time from system clock - ioc sum-d 0 ns t sdp input set-up to pclk clock - ioc sum-d 15 (t ia + t al + t lc + t sk - t pk ) 7 ns t hdp input hold time from pclk clock - ioc sum-d 0 ns t ck system-clock delay to lcc/ioc/inc 6 ns t cw system-clock low or high pulse width 7 ns f max1 max. system-clock frequency int/int 1/(t sci + t coi ) 66.6 mhz f max2 max. system-clock frequency ext/int 1/(t scx + t coi ) 58.8 mhz f max3 max. system-clock frequency int/ext 1/(t sci + t cox ) 50.0 mhz f max4 max. system-clock frequency ext/ext 1/(t scx + t cox ) 45.4 mhz f tgl max. system-clock toggle frequency 1/(t cw + t cw ) 9 71.4 mhz t pr lcc presents/reset to lcc output 1 ns t st input to global cell present/reset (t ia + t al + t pr ) 15 ns t aw asynch. preset/reset pulse width 8 ns t rt input to lcc reg-type (rt) 8 ns t rtv lcc reg-type to lcc output register change 1 ns t rtc input to global cell register-type change (t rt + t rtv ) 9 ns t rw asynch. reg-type pulse width 10 ns t reset power-on reset time for registers in clear state 2 5 s to find out if the package you need is available, contact customer service
anachip corp. www.anachip.com.tw rev. 1.0 dec 16, 2004 9/10 figure 16. sequential timing ? waveforms and block diagram notes 1. minimum dc input is -0.5v, however inputs may under-shoot to -2.0v for periods less than 20ns. 2.test points for clock and v cc in t r ,t f ,t cl ,t ch , and t reset are referenced at 10% and 90% levels. 3. i/o pins are 0v or v cc . 4. test one output at a time for a duration of less than 1 sec. 5. capacitances are tested on a sample basis. 6. test conditions assume: signal trans ition times of 5ns or less from the 10% and 90% points, timing reference levels of 1.5v (unless otherwise specified). 7. t oe is measured from input transition to v ref 0.1v (see test loads at end of section 6 for v ref value). t od is measured from input transition to v oh -0.1v or v ol +0.1v. 8. dip: ?system-clock? refers to pin 1/21 high speed clocks. plcc: ?sys- tem-clock? refers to pin 2/24 high speed clocks. 9. for t or jk registers in toggle (divide by 2) operation only. 10. for combinatorial and async-clock to lcc output delay. 11. icc for a typical application: this parameter is tested with the device programmed as a 10-bit d-type counter. 12. test loads are specified in section 5 of this data book. 13. ?async. clock? refers to the clock from the sum term (or gate). 14. the ?lcc? term indicates that the timing parameter is applied to the lcc register. the ?lcc/ioc? term indicates that the timing parameter is applied to both the lcc and ioc registers. the ?lcc/ioc/inc? term indicates that the timing parameter is applied to the lcc, ioc, and inc registers. 15. this refers to the sum-d gate routed to the ioc register for an additional buried register. 16. the term ?input? without any reference to another term refers to an (external) input pin. 17. the parameter t spi indicates that the pclk signal to the ioc register is always slower than the data from the pin or input by the absolute value of (t sk -t pk -t ia ). this means that no set-up time for the data from the pin or input is required, i.e. the external data and clock can be sent to the device simultaneously . additionally, the data from the pin must remain stable for t hpi time, i.e. to wait for the pclk signal to arrive at the ioc register. 18. typical (typ) icc is measured at t a = 25 c, freq = 25mhz, v cc = 5v to find out if the package you need is available, contact customer service
anachip corp. www.anachip.com.tw rev. 1.0 dec 16, 2004 10/10 table 6. ordering information part number speed temperature package pa7572p-20 (l) p40 pa7572f-20 (l) f44 pa7572j-20 (l) 13/20ns c j44 pa7572pi-20 (l) p40 pa7572fi-20 (l) f44 pa7572ji-20 (l) 13/20ns i j44 figure 17. part number device suffix pa7572j-20x package p = 600mil dip f = thin quad flat pack (tqfp) temperature range (blank) = commercial 0 to 70 o c i = industrial -40 to +85 o c speed -20 = 13ns/20ns tpd/tpdx lead free blank : normal l : lead free package j = plastic (j) leaded chip carrier (plcc) anachip corp. head office, 2f, no. 24-2, industry e. rd. iv, science-based industrial park, hsinchu, 300, taiwan tel: +886-3-5678234 fax: +886-3-5678368 anachip usa 780 montague expressway, #201 san jose, ca 95131 tel: (408) 321-9600 fax: (408) 321-9696 email: sales_usa@anachip.com website: http://www.anachip.com ?2004 anachip corp. anachip reserves the right to make changes in specifications at any time and wit hout notice. the information furnished by anachip in this publication is believed to be accurate and reli able. however, there is no resp onsibility assumed by anachip for its use nor for any infringements of pa tents or other rights of third parties resu lting from its use. no license is granted under any patents or patent rights of anachi p. anachip?s products are not authorized for use as critical components in life support devices or systems. marks bearing ? or ? are registered trademar ks and trademarks of anachip corp. to find out if the package you need is available, contact customer service
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